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Look at the number of patents covering every possible application of memristors. It's sick. No one ever created any practical and working device, yet those greedy bastards patented every aspect of it.

If this is true and really a new basic component of electronics, than this will be of huge impact. Especially the new way of using flux instead of voltage will alter the calculations and design of circuits. I'm not knowledgeable enough to understand all the implications, but I understand that this will have positive consequences for many types of devices.

A device with the density of a hard drive (hundreds of gigabytes or even terabytes), and the speed of dram, we could potentially assign some space for working memory (now named ram) and the rest for "storage".

Think of this:

For normal everyday use, we "only" dedicate 4 or 8 gb for "ram".
Today we are going to work with HD video, so we use 32gb of free space as "ram", and the rest of the device as storage.

Or even better, the "storage" is fast enough that we don't need to have "ram" in the middle.

Edited 2008-05-02 00:09 UTC

They can pack 100Gbits stuff into a die the same size as the highest density ever Flash die with only 16Gbits.. That's over 5 times more in the same size. That's remarkable. Also worth of note is that these memristors get ever more efficient the smaller they get whereas transistors get worse and worse. That's a huge thing really, one can only wonders how much this will change the electronical world from on. It'll take several years before these memsistors start appearing wide-spread in consumer products, but we'll likely see even hundreds of terabytes on a single storage product, ever more fast processor and god knows what more. I for one am really excited!

But, this leads me to think a little...If one can craft a storage media that can hold it's contents even after being shut down yet it has the speeds of DRAM..It sure would make sense to use that for both storing your files and using that also as RAM memory. But that would render regular PC architecture obsolete. PCs are built around separate RAM memory and storage, not a combined interface. So, what will happen? Will some new architecture rise from this new development and eventually replace PCs, or will the industry keep dragging its legs and try to maintain backwards compatibility while sacrificing the new possibilities?

They MUST rename is to flux capacitor!

Hi all,

Nice discussion.

Let's say that the memristor is to electronics what the Higgs' boson is to particle physics :-) (which is the Holy Graal of the LHC CERN experience ;-)

In 2001 I attended a plenary lecture of Leon Chua in a Circuit Theory and Design Conference. The main subject was (as far as I remember) the possibilities that quantum devices would bring to computer power. The memristor will have some quantum explanation I suspect... Anyway, what Chua was talking about was devices that would behave like switches and would not consume any (or infinitesimal) power. (the maths involved had to do with Hamiltoneans and Lagrangeans in Physics... as far as I know Chua has not published about this subject).

So, as dynamic power in CMOS is proportional to frequency*Node_capacity*Voltage**2, and is one of the current bottlenecks associated with Moore's law, one nice question is what about the energy balance in the memristor? (besides the integration density for doing memory.)

And will the memristor be used as a switch? In fact it behaves as a charge-controlled resistor (according to the Nature paper from the HP guys, pointed by the Wikipedia article http://dx.doi.org/10.1038%2Fnature06932 ), which means the resistance can be modulated and, thus, some kind of switch can be realized.

Final note: Chua is a very respected scientist in the circuit theory and simulation area. In fact he is (among other books) co-author (with Pei-Min Lin) of one book, from 1975! (I think...) which is still known as "the Kama Sutra of Circuit Simulation". Of course, someone who writes a Kama Sutra has the right to discover a new fundamental electronic device :-))

Regards,

JA

Edited 2008-05-03 00:03 UTC

the biggest question for me is, does it eliminate the limited number of writes that a flash drive has?

OSNews is not where EE chip guys hang out. Try physorg.com and sciencedaily.com or perhaps EETimes.com to get a glimpse of future technology.

Now Memristors may or may not be interesting, I will reserve my judgement on that till I do more research, but I wouldn't bank on such a huge paradigm shift occurring too soon. In the 60s we had tunnel diodes, in the 70s we had magnetic bubbles. In the 80s some thought gallium arsenide would replace silicon because of it's much higher mobility. None of these really panned out. Turns out silicon is to microchips what carbon is to life, it just works and keeps on evolving.

I spent 30 years in chip design, saw silicon go through huge improvements from 3um to far below 100nm and all that was achieved though literally thousands of minute incremental improvements usually applied 1 step at a time, very few giant changes.

You know what is most exciting to me even though I will never work on it, Nano technology, specifically Graphene. Just reading up on that on Physorg and Science Daily. It seems that Graphene would allow devices fabricated on that to have 100 times the mobility of silicon. Also could likely replace indium used in transparent conducting layers for LCDs, Solar PV cells, (indium runs out in 10yrs so a replacement is urgent).

Its going to be a Nano world and I really wish I could be young again. In the classic movie the Graduate, the young man was told to go into "Plastics". Today that would be "Nano" and "Bio" in all forms for information and energy future.


some tidbits about memory design, wikipedia probably has more content.

Memory cells DRAM, EEROM, and SRAM are laid out in regular patterns by repeatedly stepping the cell image over & over in 2 dimensions.

The highest density devices, DRAM, NAND/NOR EEPROM (Flash etc) all require about 4 to 8 squares of geometry to make a 3 terminal transistor (a 1 t cell). The more the transistor shares features with a neighbor, the smaller the cell can be, but the more overhead there must be further away. In the SRAM cell, the 6t cell is most complete but enormously larger than 8 squares (varies from 100-500 squares), but that gives differential high speed sensing along with a great amount of leakage over a large enough area,

Right now Flash has the highest density (see 16GB devices) but still is limited by the ability to pattern vertical metal bit lines over word row lines, every intersection gives 1 device in the serial NAND version and for every 8 or so bits there is some overhead added to read that segment. The NOR version is somewhat less dense, it is really a 1b NAND with the read overhead per bit. Apparent density can be increased by storing 2 or more bits per Flash cell for much lower performance though.

DRAM is a little different in that the 3rd terminal is to a vertical capacitor node usually buried in some fashion and these cells are less dense than Flash hence 1GB DRAM chips.

Usually DRAM is understood to be slow and SRAM fast. Some DRAM can be quite fast if the overhead is increased somewhat, I saw IBM designs a decade ago that were 5ns and I think they can now do 2ns cycles while commodity DRAMs that sit on PC DIMMs usually cycle in 60ns. Some SRAM can be quite slow, when you build large memory arrays, the much longer interconnect limits how fast the array can be driven. DRAM can win because the cells are more densely packed but the DRAM process is not really compatible with processor processes so SRAM is used despite its limits. Putting DRAM onto a processor would allow bigger caches but the process and hence clock speed would be much slower.

DRAM is best used in large arrays for density and low power but can be used for fast L3 cache if desired in modified processes.

SRAM is really best used when lots of small memories are needed where the overhead needs to be more limited. In FPGAs SRAM gives one tremendous aggregate I/O bandwidth, example having 500 independent SRAMs all doing something useful per clock. In processor designs the SRAMs are fewer but much larger, there's only so much parallelism available.